This invention relates to a clock distribution system of a computer or the like, and more particularly to a clock distribution system which will is suitable for use in a clock distribution system of a computer for processing operations at a high speed.
An example of a clock distribution system of a conventional computer is shown in FIG. 2. In FIG. 2, reference numeral 10 represents a clock generation block, 50 is a processing unit (which will be hereby assumed as LSI) which is the destination of distribution of the clock generation block, and 30 identifies signal paths connecting the clock generation block 10 to the processing unit 50 (such as wirings on a substrate or cables). Terminal distribution destinations (e.g. flip-flop 46) exist inside the processing unit 50. This clock distribution system divides the frequency of high frequency signals generated by a generator 11 into the necessary frequency and corresponding clock signals by a frequency divider 12, distributes the clock signals to each processing unit through a distribution circuit 13 and the signal paths 30, and distributes them further to the flip-flop 46 through an input buffer 40, a distribution circuit 43 and wirings 45 inside each processing unit. The conventional clock distribution system involves the following two problems.
First of all, if the signal propagation delay of the distribution circuit 13, the signal paths 30, the input buffer 40, the distribution circuit 45 and the wiring 45 is different between the processing units 50, clock skew (phase variance of clock signals) in the flip-flop 46 occurs. If this clock skew is great, a problem exists regarding a high speed operation of the computer because each processing unit 50 operates in synchronism with the clock signals.
Secondly, if the frequency of the clock signal distributed to each processing unit 50 is high or the pulse width is small, influences of reflection occurring when it passes through the wirings on the substrate or the cables and damping of amplitude become great. It is therefore difficult to distribute those clock signals which have a high frequency and a small pulse width.
To cope with the first problem, an attempt has been made to reduce clock skew by adjusting the phases of clock signals. As a phase adjustment method of clock signals in a conventional computer, a method is known which disposes a delay at an intermediate part of each signal path 30 shown in FIG. 2, the waveform of the clock signal at each destination is observed by use of an oscilloscope and manually the delay is adjusted so as to match the phase with a set value. Japanese Patent Laid-Open No. 39650/1986 discloses a method which eliminates the necessity of adjusting the delays by changing the delay time of the delay by use of control signals. As a method which does not use the oscilloscope, Japanese Patent Laid-Open No. 39619/1986 discloses a method which constitutes a ring oscillator by clock distribution circuits, detects the signal delay time of the clock distribution circuit from its oscillation frequency and matches it with the stipulated value.
The second problem can be solved, in principle, by disposing a circuit which generates a high frequency signal in each processing unit and generating desired clock signals from the output of the circuit. For example, a clock signal having a relatively low frequency is inputted from outside, a high frequency signal is generated from this clock signal by a PLL circuit and a multi-phase clock signal is generated by use of this high frequency signal. Japanese Patent Laid-Open No. 21919/1988 discloses a method which generates a clock signal synchronized with an external clock signal by use of a ring oscillator.
If the phase adjustment of the clock signals is made by use of the oscilloscope or the like to cope with the first problem, a great deal of time and labor is necessary for the adjustment and the adjustment is limited. Therefore, once the phase adjustment is made at a limited number of relay points, the clock signals must be sent to the terminal destination without adjustment. Variance of the signal propagation delay at these points, where the signals are sent without adjustment, limits reduction of clock skew. Particularly in the case of a LSI containing CMOS circuits in the clock distribution system, variance of the delay time due to processors or the like is great so that the clock signals inputted to the flip-flops inside LSI as the terminal destination have to great skew.
The method disclosed in Japanese Patent Laid-Open No. 39650/1986 eliminates the necessity of changing delays. But the clock signal phase must be observed to determine if the desired phase is present. Since the delay time is controlled by an analog voltage, this analog voltage produces the clock skew if it changes due to noise. In accordance with the method disclosed in Japanese Patent Laid-Open No. 39619/1986, the propagation times of the signal paths for feeding back the signal from each destination to the original input point must all be aligned. After all, therefore, the clock skew cannot be reduced unless the propagation time of a large number of signal paths is aligned.
The method which disposes the PLL circuit in each processing unit and generates a desired clock signal by frequency-dividing its output as the solution for the second problem is not free from the problem. Since PLL circuits in general use a high level control signals, they are susceptible to noise or the like when they co-exist with a LSI. Since a high frequency signal is always used inside the processing unit, problems in reliability such as the occurrence of noise develop.
Since the method disclosed in Japanese Patent Laid-Open No. 211919/1988 generates always the high frequency signal by a ring oscillator, the problem as with the PLL circuit occurs. Though the method using the PLL circuit or the ring oscillator can synchronize the low frequency external clock signal with the clock signal generated inside LSI, since the propagation delay of the distribution circuit which distributes the resulting clock signals varies from processing unit to processing unit, the clock skew at the flip-flop at the terminal destination remains unsolved.
In the co-pending patent application Ser. No. 152,916 filed Feb. 5, 1988 by some of the inventors of the present invention, there is disclosed a clock signal supply system comprising phase adjusting circuits for automatic adjustment of the phase shift of clock signals at a multiplicity of clock signal destinations. A first signal line transmits clock signals from a clock signal source to the phase adjusting circuits. A reference signal generation circuit generates a reference signal in predetermined relationship with the clock signals. A second signal line transmits the reference signal to the phase adjusting circuits. The clock signal received through the first signal line is compared with the reference signal received through the second signal line by the phase adjusting circuit, which then adjusts the phase of the received clock signal in predetermined phase relationship with the reference signal.
Co-pending patent application Ser. No. 395,958 filed Aug. 18, 1989 by some of the co-inventors of the present invention, discloses a clock signal supplying device provided with an automatic phase regulating function for preventing error in the phase regulation due to noise. In the device according to this application, a reference signal serves as a phase reference. Transmission lines for clock signals and a transmission line for the reference signal are coupled to the device, which is a clock signal supplying source, to devices, which are destinations of the distribution of the clock signals. The transmission line for the reference signal is adjusted in advance so as to produce no skew. For example, the frequency of the reference signal is set at a low value, for which the phase regulation is easy, and all of the transmission lines for the reference signal are made uniform in phase by keeping the load condition and the length of each of the lines uniform. In the device, which is the destination of distribution of the clock signal, a variable delay circuit regulates the phase of the clock signal and a phase comparing circuit compares the output of the variable delay circuit with the phase of the reference signal and outputs the result of the comparison. The amount of delay of the variable delay circuit is controlled to the output of the phase comparing circuit. A disturbance due to noise from the exterior or the interior during the phase regulation can produce errors in the amount of the phase regulation. In the device according to the above application, a noise filter is provided, which detects phase regulation errors to correct phase regulation. Furthermore, the phase regulation is produced while avoiding a period of time where noises is likely to be produced.